1. Technical Field
The present invention relates to a test module and a test method. More specifically, the present invention relates to a test module and a test method that can dynamically generate a pseudo random pattern in response to a control instruction.
2. Related Art
For example, Japanese Patent Application Publication Nos. 06-021781 and 06-291619 disclose a pattern generator that generates pseudo random patterns in parallel or multiple channels. Generally speaking, a circuit constituted by an n-bit random number generation shift register and an exclusive OR (EOR) is used to generate a pseudo random bit sequence with a cycle of 2n−1 by taking bits indicated by an n-th-order primitive polynomial, calculating an EOR logical operation of the bits, and shifting-in the result of the EOR logical operation into the random number generation shift register.
Here, the primitive polynomial is configured by the value of a polynomial configuration register, and the random number generation shift register receives as the initial value the value of an initial value configuration register and starts the shifting on reception of the initial value.
However, the value of the polynomial configuration register or the value of the initial value configuration register cannot be dynamically changed by, for example, a control instruction. A test apparatus may employ a pseudo random pattern as a test pattern. Such a test apparatus may desire to configure the initial value to a specific value or generate the pseudo random pattern reflecting test results. These demands are preferably fulfilled.